Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
Public
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12.4. ALTFP_SINCOS Signals

Figure 34. ALTFP_SINCOS Signals
Table 70.  ALTFP_SINCOS IP Core Input Signals
Port Name Required Description
aclr No Asynchronous clear. When the aclr port is asserted high, the function is asynchronously cleared.
clk_en No Clock enable. When the clk_en port is asserted high, sine or cosine operation takes place. When the signal is asserted low, no operation occurs and the outputs remain unchanged.
clock Yes Clock input to the Intel® FPGA IP core.
data[] Yes Floating-point input data. The MSB is the sign bit, the next MSBs are the exponent, and the LSBs are the mantissa. This input port size is the total width of the sign bit, exponent bits, and mantissa bits.
Table 71.  ALTFP_SINCOS IP Core Output Signals
Port Name Required Description
result[] Yes The trigonemetric of the data[] input port in floating-point format. The widths of the result[] output port and data[] input port are the same.

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