Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
Public
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2.3. FP_ACC_CUSTOM Intel® FPGA IP Resource Utilization and Performance

Table 9.  FP_ACC_CUSTOM Intel® FPGA IP Resource Utilization and PerformanceThis table lists the resource utilization and performance information for the FP_ACC_CUSTOM Intel® FPGA IP core. The information was derived using the Intel® Quartus® Prime software version 13.1.
Device Family Input Data Accumulator Size Target Frequency (MHz) Latency ALMs DSP Blocks Logic Registers M10K M20K fMAX
Floating Point Format MaxMSBX MSBA LSBA Primary Secondary
Arria V (5AGXFB3H4F40C5) Double 24 40 -52 270 15 866 0 1,166 106 0 -- 265
Cyclone V (5CGXFC7D6F31C7) Double 24 40 -52 230 15 830 0 1,102 32 0 -- 198
Stratix V (5SGXEA7K2F40C2) Double 24 40 -52 400 15 968 0 1,655 27 -- 0 426
Arria V (5AGXFB3H4F40C5) Single 12 20 -26 270 12 337 0 588 52 0 -- 309
Cyclone V (5CGXFC7D6F31C7) Single 12 20 -26 230 12 383 0 494 28 0 -- 225
Stratix V (5SGXEA7K2F40C2) Single 12 20 -26 400 13 475 0 903 20 -- 0 450

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