Visible to Intel only — GUID: eis1411615440318
Ixiasoft
Visible to Intel only — GUID: eis1411615440318
Ixiasoft
9.5.1. ALTFP_INV_SQRT Design Example: Understanding the Simulation Results
These figures show the expected simulation results in the ModelSim* - Intel® FPGA Edition software.
![](/content/dam/docs/us/en/683750/20-1/eis1414120562243.png)
![](/content/dam/docs/us/en/683750/20-1/eis1414120629084.png)
This design example implements a floating-point inverse square root for single-precision format numbers. The optional input ports (clk_en and aclr) and all three exception handling output ports (division_by_zero, nan, and zero) are enabled.
The latency is fixed at 26 clock cycles. Therefore, every inverse square root operation outputs the results 26 clock cycles later.
This table lists the inputs and corresponding outputs obtained from the simulation in the waveforms.
Time | Event |
---|---|
0 ns, start-up | data[] value: 05AE 470Bh Output value: An undefined value is seen on the result[] port, which can be ignored. All values seen on the output port before the 26th clock cycle are merely due to the behavior of the system during start-up and should be disregarded. |
127.5 ns | Output value: 5C5B 64CEh The inverse square root of a normal number results in a normal value. |
10 ns | data[] value: E8A7 E93Dh This is a negative normal value. |
137.5 ns | Output value: FFC0 0000h Exception handling ports: nan asserts The inverse square root of a negative value produces a NaN. |
20 ns | data[] value: 0000 0004h The is a denormal value. |
147.5 ns | Output value: 7F80 0000h Denormal numbers are forced-zero values, therefore the inverse square root of zero results in infinity. Exception handling ports: nan deasserts, division_by_zero asserts |
50 ns | data[] value: 7F80 0000h This is an infinity value. |
177.5 ns | Output value: 0000 0000h The inverse square root of an infinity value produces a zero. Exception handling ports: zero asserts |