Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
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4.2. ALTFP_DIV Output Latency

The output latency options for the ALTFP_DIV IP core differs depending on the precision selected, the width of the mantissa, or both. You have the choice of selecting the smaller figures of clock cycles delay in your design if the low latency option is desired.
Table 19.  Latency Options for Each Operation 
Precision Mantissa Width Latency (in clock cycles)
Single 23 6, 14, 33
Double 52 10, 24, 61
Single Extended 31 – 32 8, 18, 41
33 – 34 8, 18, 43
35 – 36 8, 18, 45
37 – 38 8, 18, 47
39 – 40 8, 18, 49
41 10, 24, 41
42 10, 24, 51
43 – 44 10, 24, 53
45 – 46 10, 24, 55
47 – 48 10, 24, 57
49 – 50 10, 24, 59
51 – 52 10, 24, 61

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