|aclr||No||Asynchronous clear. When the aclr port is asserted high, the function is asynchronously cleared.|
Clock enable. When the clk_en port is asserted high, a natural logarithm operation takes place. When signal is asserted low, no operation occurs and the outputs remain unchanged.
Deasserting clk_en halts operation until it is asserted again. Assert the clk_en signal for the number of clock cycles equivalent to the required output latency (PIPELINE parameter value) for the results to be shown at the output.
|clock||Yes||Clock input to the IP core.|
Floating-point input data. The MSB is the sign bit, the next MSBs are the exponent, and the LSBs are the mantissa. This input port size is the total width of the sign bit, exponent bits, and mantissa bits.
For single precision, the width is fixed to 32 bits. For double precision, the width is fixed to 64 bits. For single extended precision, you can choose a width in the range from 43 to 64 bits.
|result||Yes||The natural logarithm of the value on input data. The natural logarithm of the data input port, shown in floating-point format. The widths of the result output port and data input port are the same.|
|zero||No||Zero exception output. Asserted when the exponent and mantissa of the output port are zero. This occurs when the actual input value is 1 because ln 1 = 0.|
|nan||No||NaN exception output. Asserted when the exponent and mantissa of the output port are all 1’s and non-zero, respectively. This occurs when the input is a negative number or NaN.|
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