Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
Public
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14.5. ALTFP_COMPARE Signals

Figure 38. ALTFP_COMPARE Signals
Table 80.  ALTFP_COMPARE Input Signals
Port Name Required Description
aclr No Asynchronous clear. The source is asynchronously reset when asserted high.
clk_en No Clock enable. When this port is asserted high, a compare operation takes place. When signal is asserted low, no operation occurs and the outputs remain unchanged.
clock Yes Clock input to the IP core.
dataa[] Yes Data input. The MSB is the sign bit, the next MSBs are the exponent, and the LSBs are the mantissa. This input port size is the total width of sign bit, exponent bits, and mantissa bits.
datab[] Yes Data input. The MSB is the sign bit, the next MSBs are the exponent, and the LSBs are the mantissa. This input port size is the total width of sign bit, exponent bits, and mantissa bits.
Table 81.  ALTFP_COMPARE Output Signals
Port Name Required Description
aeb Yes Output port for the comparator. Asserted if the value of the dataa[] port equals the value of the datab[] port.
agb Yes Output port for the comparator. Asserted if the value of the dataa[] port is greater than the value of the datab[] port.
ageb Yes Output port for the comparator. Asserted if the value of the dataa[] port is greater than or equal to the value of the datab[] port.
alb Yes Output port for the comparator. Asserted if the value of the dataa[] port is less than the value of the datab[] port.
aleb Yes Output port for the comparator. Asserted if the value of the dataa[] port is less than or equal to the value of the datab[] port.
aneb Yes Output port for the comparator. Asserted if the value of the dataa[] port is not equal to the value of the datab[] port.
unordered Yes Output port for the comparator. Asserted when either the dataa[] port and the datab[] port is set to NaN, or if both the dataa[] port and the datab[] port are set to NaN.

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