Floating-Point IP Cores User Guide

Download
ID 683750
Date 9/13/2021
Public
Document Table of Contents

8.6. Ports

Table 48.  ALTFP_INV IP core Input Ports
Port Name Required Description
aclr No Asynchronous clear. When the aclr port is asserted high, the function is asynchronously cleared.
clk_en No Clock enable. When the clk_en port is asserted high, an inversion value operation takes place. When signal is asserted low, no operation occurs and the outputs remain unchanged.
clock Yes Clock input to the IP core.
data[] Yes Floating-point input data. The MSB is the sign, the next MSBs are the exponent, and the LSBs are the mantissa. This input port size is the total width of the sign bit, exponent bits, and mantissa bits.
Table 49.  ALTFP_INV IP core Output Ports
Port Name Required Description
result[] Yes The floating-point inverse result of the value at the data[]input port. The MSB is the sign, the next MSBs are the exponent, and the LSBs are the mantissa. The size of this port is the total width of the sign bit, exponent bits, and mantissa bits.
underflow No Underflow exception output. Asserted when the result of the inversion (after rounding) is a denormalized number.
zero No Zero exception output. Asserted when the value at the result[] port is a zero.
division_by_zero No Division-by-zero exception output. Asserted when the denominator input is a zero.
nan No NaN exception output. Asserted when an invalid inversion occurs, such as the inversion of NaN. In this case, a NaN value is output to the result[] port. Any operation involving NaN also asserts the nan port.

Did you find the information on this page useful?

Characters remaining:

Feedback Message