Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
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4.6. ALTFP_DIV Signals

Figure 18. ALTFP_DIV Signals
Table 23.  ALTFP_DIV Input Signals
Port Name Required Description
aclr No Asynchronous clear input for the floating-point divider. The source is asynchronously reset when the aclr signal is asserted high.
clock Yes Clock input to the IP core.
clk_en No Clock enable to the floating-point divider. This port enables division. This signal is active high. When this signal is low, no division takes place and the outputs remain the same.
dataa[] Yes Numerator data input. The MSB is the sign bit, the next MSBs are the exponent, and the LSBs are the mantissa. The size of this port is the total width of the sign bit, exponent bits and mantissa bits.
datab[] Yes Denominator data input.The MSB is the sign bit, the next MSBs are the exponent, and the LSBs are the mantissa. The size of this port is the total width of the sign bit, exponent bits and mantissa bits.
Table 24.  ALTFP_DIV Output Signals
Port Name Required Description
result[] Yes Divider output port. The division result (after rounding). As with the input values, the MSB is the sign, the next MSBs are the exponent, and the LSBs are the mantissa. The size of this port is the total width of the sign bit, exponent bits, and mantissa bits.
overflow No Overflow port for the divider. Asserted when the result of the division (after rounding) exceeds or reaches infinity. Infinity is defined as a number in which the exponent exceeds 2WIDTH_EXP–1.
underflow No Underflow port for the divider. Asserted when the result of the division (after rounding) is zero even though neither of the inputs to the divider is zero, or when the result is a denormalized number.
zero No Zero port for the divider. Asserted when the value of result[] is zero.
division_by_zero No Division-by-zero output port for the divider. Asserted when the value of datab[] is a zero.
nan No NaN port. Asserted when an invalid division occurs, such as infinity dividing infinity or zero dividing zero. A NaN value appears as output at the result[] port. Any division of a NaN value causes the nan output port to be asserted.

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