Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
Public
Document Table of Contents

1.5. Floating-Point IP Cores General Features

All Intel FPGA floating-point IP cores offer the following features:
  • Support for floating-point formats.
  • Input support for not-a-number (NaN), infinity, zero, and normal numbers.
  • Optional asynchronous input ports including asynchronous clear (aclr) and clock enable (clk_en).
  • Support for round-to-nearest-even rounding mode.
  • Compute results of any mathematical operations according to the IEEE-754 standard compliance with a maximum of 1 unit in the last place (u.l.p.) error. This assumption is applied to all floating-point IP cores.

Intel FPGA floating-point IP cores do not support denormal number inputs. If the input is a denormal value, the IP core forces the value to zero and treats the value as a zero before going through any operation.

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