Floating-Point IP Cores User Guide

ID 683750
Date 9/13/2021
Document Table of Contents

16.6. FP_FUNCTIONS Intel® FPGA IP Signals

Figure 41. FP_FUNCTIONS Intel® FPGA IP Signals
Table 97.  FP_FUNCTIONS Intel® FPGA IP Input Signals
Port Name Required Description
clk Yes All input signals must be synchronous to this clock.
areset Yes Asynchronous active-high reset. Deassert this signal synchronously to the input clock to avoid metastability issues.
en No

Optional port. Allow calculation to take place when asserted. When deasserted, no operation will take place and the outputs are unchanged.

a Yes Data input signal.
b Yes Data input signal (where applicable).
s Yes Select port for Add/Sub function.
c Yes Data port for integer exponent port for LDExp function.
Table 98.  FP_Functions Intel FPGA IP Output Signals
Port Name Required Description
q Yes Data output signal.

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