Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
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2.4. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Signals

Figure 14. FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP
Table 10.  FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Input Ports
Port Name Required Description
clk Yes All input signals, otherwise explicitly stated, must be synchronous to this clock
areset Yes Asynchronous active-high reset. Deassert this signal synchronously to the input clock to avoid metastability issues.
en No Global enable signal. This port is optional.
x Yes Data input port.
n Yes Boolean port which signals the beginning of a new data set to be accumulated. This should go high together with the first element in the new data set and should go low the next cycle. The data sets may be of variable length and a new data set may be started at any time. The accumulation result for an input is available after the reported latency.
Table 11.  FP_ACC_CUSTOM Intel® FPGA IP or Floating Point Custom Accumulator Intel® FPGA IP Output Ports
Port Name Required Description
r Yes The running value of the accumulation.
xo Yes The overflow flag for port x. The signal goes high when the exponent of the input x is larger than maxMSBX. The signal remains high for the entire data set. This flag invalidates port r. You should consider increasing maxMSBX. This flag also indicate infinity and NaN.
xu Yes The underflow flag for port x. The signal goes high when the exponent of the input x is smaller than LSBA. The signal remains high for the entire data set. This flag does not invalidate port r. You should consider lowering LSBA.
ao Yes The overflow flag for Accumulator. The signal goes high when the exponent of the accumulated value is larger than MSBA. The signal remains high for the entire data set. This flag invalidates port r. You should consider increasing MSBA.

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