Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
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11.4. Ports

Table 67.  ALTFP_ATAN IP core Input Ports
Port Name Required Description
aclr No Asynchronous clear. When the aclr port is asserted high, the function is asynchronously cleared.
clk_en No Clock enable. When the clk_en port is asserted high, division takes place. When the signal is deasserted, no operation occurs and the outputs remain unchanged.
clock Yes Clock input to the IP core.
data[] Yes Floating-point input data. The MSB is the sign bit, the next MSBs are the exponent, and the LSBs are the mantissa. This input port size is the total width of the sign bit, exponent bits, and mantissa bits.
Port Name Required Description
result[] Yes The result of the trigonometric function in floating-point format. The widths of the result[] output port and data[] input port are the same.

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