7.5.1. ALTFP_EXP Design Example: Understanding the Simulation Results
These figures show the expected simulation results in the ModelSim* - Intel® FPGA Edition software.
This design example implements a floating-point exponential for the single-precision format numbers. The optional input ports (clk_en and aclr) and all four exception handling output ports (nan, overflow, underflow, and zero) are enabled.
For single-precision format numbers, the latency is fixed at 17 clock cycles. Therefore, every exponential operation outputs the results 17 clock cycles later.
|0 ns, start-up|| data value: 1A03 568Ch
Output value: An undefined value is seen on the result port, which is ignored. All values seen on the output port before the 17th clock cycle are merely due to the behavior of the system during start-up and should be disregarded.
|82.5 ns||Output value: 3F80 0000h
As the input value of 1A03568Ch is a very small number, it is seen as a value that is approaching zero, and the result approaches 1 (which is represented by 3F800000). Exponential operations carried out on numbers of very small magnitudes result in a 1 and assert the underflow flag.
Exception handling ports: underflow asserts
|30 ns|| data value: F3FC DEFFh
This is a normal negative value of a very large magnitude.
|112.5 ns||Output value: 0000 0000h
The outcome of exponential operations on negative numbers of very large magnitudes approaches zero.
Exception handling ports: underflow remains asserted
|60 ns|| data value: 7F80 0000h
This is a positive infinite value.
|142.5 ns||Output value: 7F80 0000h
The operation on positive infinite values results in infinity.
Exception handling ports: underflow deasserts, overflow asserts
|90 ns|| data value: 7FC0 0000h
This is a NaN.
|172.5 ns||Output value: 7FC0 0000h
The exponential of a NaN results in a NaN.
Exception handling ports: nan asserts
|120 ns|| data value: C1D4 49BAh
This is a normal value.
|202.5 ns||Output value: 2C52 5981h
The result is a normal value.
Exception handling ports: nan deasserts
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