Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
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7.6. ALTFP_EXP Signals

Figure 25. ALTFP_EXP Signals
Table 42.  ALTFP_EXP IP Core Input Signals
Port Name Required Description
aclr No Asynchronous clear. When the aclr port is asserted high the function is asynchronously reset.
clk_en No Clock enable. When the clk_en port is asserted high, an exponential value operation takes place. When this signal is asserted low, no operation occurs and the outputs remain unchanged.
clock Yes Clock input to the IP core.
data[] Yes Floating-point input data. The MSB is the sign, the next MSBs are the exponent, and the LSBs are the mantissa. This input port size is the total width of the sign bit, exponent bits, and mantissa bits.
Table 43.  ALTFP_EXP IP Core Output Signals
Port Name Required Description
result[] Yes The floating-point exponential result of the value at data[]. The MSB is the sign, the next MSBs are the exponent, and the LSBs are the mantissa. The size of this port is the total width of the sign bit, exponent bits, and mantissa bits.
overflow No Overflow exception output. Asserted when the result of the operation (after rounding) is infinite.
underflow No Underflow exception output. Asserted when the result of the exponential approaches 1 (from numbers of very small magnitude), or when the result approaches 0 (from negative numbers of very large magnitudes).
zero No Zero exception output. Asserted when the value in the result[] port is zero.
nan No NaN exception output. Asserted when an invalid operation occurs. Any operation involving NaN also asserts the nan port.

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