10.5.1. ALTFP_LOG Design Example: Understanding the Simulation Results
These figures show the expected simulation results in the ModelSim* - Intel® FPGA Edition software.
This design example includes the input of special cases to show the exception handling of the IP core, such as the smallest valid input and the input value of “1”.
In this example, the output delay is set to 21 clock cycles. Therefore, the result is only shown at the output port after the 21st clock cycle at 102.5 ns.
|0 ns, start-up|| data value: 0000 0000h
Output value: An undefined value is seen on the result port, which is ignored. All values seen on the output port before the 21st clock cycle are merely due to the behavior of the system during start-up and should be disregarded.
|102.5 ns||Output value: FF80 0000h
The natural logarithm of zero is negative infinity.
|5 ns|| data value: 8000 0000h
This is a negative number.
|107.5 ns||Output value: FFC0 0000h
Exception handling ports: nan asserts
The natural logarithm of a negative value is invalid. Therefore, the output produced is a NaN.
|30 ns|| data value: 0040 0000h
The is a denormal value.
|132.5 ns||Output value: FF80 0000h
As denormal numbers are not supported, the input is forced to zero before going through the logarithm function. The natural logarithm of zero is negative infinity.
|45 ns|| data value: 0080 0000h
This is the smallest valid input. All the input bits are 0 except the LSB of the exponent field.
|147.5 ns||Output value: C2AE AC50h|
|60 ns|| data value: 3F80 0000h
The input value 3F80 0000h is equivalent to the actual value, 1.0 × 20 = 1.
|152.5 ns||Output value: 0000 0000h
Exception handling ports: zero asserts
Since In 1 results in zero, it produces an output of zero.
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