Floating-Point IP Cores User Guide

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ID 683750
Date 9/13/2021
Public
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3.6. ALTFP_ADD_SUB Signals

Figure 16. ALTFP_ADD_SUB
Table 16.  ALTFP_ADD_SUB Input Ports
Port Name Required Description
aclr No Asynchronous clear input for floating-point adder or subtractor. The source is asynchronously reset when the aclr signal is asserted high.
add_sub No Optional input port to enable dynamic switching between the adder and subtractor functions. The add_sub port must be used when the DIRECTION parameter is set to VARIABLE. When the add_sub port is high, result[] = dataa[] + datab[], otherwise, result[] = dataa[] - datab[].
clk_en No Clock enable to the floating-point adder or subtractor. This port allows addition or subtraction to occur when asserted high. When asserted low, no operations occur and the outputs are unchanged.
clock Yes Clock input to the IP core.
dataa[] Yes Data input to the floating-point adder or subtractor. The MSB is the sign bit, the next MSBs are the exponent, and the LSBs are the mantissa bits. The size of this port is the total width of the sign bit, the exponent bits, and the mantissa bits.
datab[] Yes Data input to the floating-point adder or subtractor. This port is configured in the same way as dataa[].
Table 17.  ALTFP_ADD_SUB Output Ports
Port Name Required Description
nan Yes NaN exception output. Asserted when an illegal addition or subtraction occurs, such as infinity minus infinity. When an invalid addition or subtraction occurs, a NaN value is output to the result[] port. Any adding or subtracting involving NaN values also produces a NaN value.
overflow Yes Overflow exception port. Asserted when the result of the addition or subtraction, after rounding, exceeds or reaches infinity. Infinity is defined as a number in which the exponent exceeds 2 WIDTH_EXP -1.
result[] Yes Floating-point output result. Like the input values, the MSB is the sign, the next MSBs are the exponent, and the LSBs are the mantissa. The size of this port is the total width of the sign bit, exponent bits, and mantissa bits.
underflow Yes Underflow port for the adder or subtractor. Asserted when the result of the addition or subtraction, after rounding, the value is zero and the inputs are not equal. The underflow port is also asserted when the result is a denormalized number.
zero No Zero port for the adder or subtractor. Asserted when the result[] port is zero.

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