External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

4.1.4.17. emif_usr_clk for QDR-IV

User clock interface

Table 127.  Interface: emif_usr_clkInterface type: Clock Output
Port Name Direction Description
emif_usr_clk Output User clock domain