Visible to Intel only — GUID: hco1410185629514
Ixiasoft
Design Hierarchy and safety IP partitions
Preparing the Design Example in the Intel® Quartus® Prime Software
DC Link Monitor safety IP partition
Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component
Creating a Safety IP partition for the PWM Interface Component
Creating a Safety IP LogicLock Region for the DC Link Monitor
Creating a LogicLock Region for the PWM Interface
Creating a Fixed Size and Origin for a LogicLock Region
Removing Precomiled Netlists
Using the Intel® Quartus® Prime Incremental Compilation
Compiling the Design
The Fitter Report
Exporting Safety IP Partition
Generating Safety IP Bitstream Files
Visible to Intel only — GUID: hco1410185629514
Ixiasoft
Using the Intel® Quartus® Prime Incremental Compilation
Using this feature on the nonsafety IP partitons in the design does not interfere with strictly preserved safety IP partitions.
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