AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

ID 683720
Date 9/01/2018
Document Table of Contents

Creating a Safety IP LogicLock Region for the DC Link Monitor

To fix the safety IP into specific areas of the device, define LogicLock regions. By using preserved LogicLock regions, the Intel® Quartus® Prime software reserves device placement for the safety IP. LogicLock regions prevent the Intel® Quartus® Prime software from placing nonsafety IP into the unused resources of the safety IP region. You establish a fixed size and origin to ensure location preservation.
  1. Create a new LogicLock region.
    1. In the Project Navigator, right-click on the entity DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link:doc_safe_pll_dc_link
    2. Click LogicLock Region > Create New LogicLock Region
  2. Open the LogicLock Regions window:
    1. In the Project Navigator, select the entity DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link:doc_safe_pll_dc_link
    2. Right-click and select LogicLock Region > LogicLock Regions Window.
  3. Set a fixed size and origin for the safety IP partition:
    1. In the LogicLock Regions window, right-click the region DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link:doc_safe_pll_dc_link
    2. Select LogicLock Regions Properties
    3. Turn on Reserved (Prevent Fitter from placing non-member logic in region).
    4. On the Size and Origin tab, choose a fixed size and origin for the region. You may select your own values, however width = 7, height = 5, origin = X7_Y34 are suitable values.