AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

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ID 683720
Date 9/01/2018
Public
Document Table of Contents
Document Table of Contents x
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification x
About the Functional Safety Separation Flow Work Flows Functional Safety Separation of a Motor Control Design Example Appendix A: Terminology Appendix B: Design Checklist Document Revision History for AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
Work Flows x
Design Creation Flow Design Modification Flow
Functional Safety Separation of a Motor Control Design Example x
Design Considerations Design Creation Flow Using the Design Modification Flow
Design Considerations x
About Safety IP Partitions and LogicLock Regions Assigning I/O Pins Clocks, PLLs and Resets Routing Across Safety IP Partitions
Design Creation Flow x
Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Using the Intel® Quartus® Prime Incremental Compilation x
Creating a Partition for the FOC Fixed-Point Component Creating a LogicLock Region for the FOC Fixed-Point Component
Generating Safety IP Bitstream Files x
Generating Complete FPGA Bitstream File
Using the Design Modification Flow x
Changing Nonsafety IP - Changing FOC Algorithm Parameter Adding New Features to Nonsafety IP Importing Safety IP Partition
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

Creating a Safety IP LogicLock Region for the DC Link Monitor

To fix the safety IP into specific areas of the device, define LogicLock regions. By using preserved LogicLock regions, the Intel® Quartus® Prime software reserves device placement for the safety IP. LogicLock regions prevent the Intel® Quartus® Prime software from placing nonsafety IP into the unused resources of the safety IP region. You establish a fixed size and origin to ensure location preservation.
  1. Create a new LogicLock region.
    1. In the Project Navigator, right-click on the entity DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link:doc_safe_pll_dc_link
    2. Click LogicLock Region > Create New LogicLock Region
  2. Open the LogicLock Regions window:
    1. In the Project Navigator, select the entity DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link:doc_safe_pll_dc_link
    2. Right-click and select LogicLock Region > LogicLock Regions Window.
  3. Set a fixed size and origin for the safety IP partition:
    1. In the LogicLock Regions window, right-click the region DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link:doc_safe_pll_dc_link
    2. Select LogicLock Regions Properties
    3. Turn on Reserved (Prevent Fitter from placing non-member logic in region).
    4. On the Size and Origin tab, choose a fixed size and origin for the region. You may select your own values, however width = 7, height = 5, origin = X7_Y34 are suitable values.
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