AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

ID 683720
Date 9/01/2018
Document Table of Contents

Functional Safety Separation of a Motor Control Design Example

A simplified motor control system demonstrates the functional safety separation flow. Intel derived this system from the Intel Drive-On-Chip Reference Design. The Drive-On-Chip design demonstrates concurrent multi-axis control of up to 4 three phase AC 400V permanent magnet synchronous motors (PMSMs) or brushless DC (BLDC) motors, and supports many combinations of device, development board, power board, and design parameterizations.

For the functional safety IP partition flow, Intel removes the following items from the Drive-On-Chip reference design for the simplified motor control system:

  • Intel® Quartus® Prime project revisions
  • # defines in the top level design file leaving support for one development platform configuration
  • OpenCore Plus licensed IP (enDAT and BISS encoder interface components). You require full licenses to use the functional safety separation flow

This design example only demonstrates the functional safety separation flow. The design example is not fully functional and does not run on a hardware platform

Figure 6. Motor Control Design Example Block DiagramThe PLL provides clocks to all blocks in the Qsys system and the external ADC.