Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Appendix A: Terminology
A LogicLock region is a physical partition or type of placement constraint in the Intel® Quartus® Prime software. You can define any arbitrary region of physical resources on the target device as a LogicLock region. A LogicLock region can have the following size and location settings:
|Validation||The DUT is performing the correct operation versus the high-level requirements.|
|Verification||The DUT operation is correct versus the module design and test specification.|
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