Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
About Safety IP Partitions and LogicLock Regions
Intel recommends that you do not overlap any reserved LogicLock regions. The Intel® Quartus® Prime Fitter does not use overlapping areas. The chip planner checks for overlapping regions.
You must not create safety IP partitions as sub-partitions of another safety partition. If you create a safety IP partition and then place a safety IP partition inside that partition, the Intel® Quartus® Prime software does not achieve strict preservation. The design modification flow detects this preservation failure.
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