AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

ID 683720
Date 9/01/2018
Document Table of Contents

About Safety IP Partitions and LogicLock Regions

Intel recommends that you do not overlap any reserved LogicLock regions. The Intel® Quartus® Prime Fitter does not use overlapping areas. The chip planner checks for overlapping regions.

You must not create safety IP partitions as sub-partitions of another safety partition. If you create a safety IP partition and then place a safety IP partition inside that partition, the Intel® Quartus® Prime software does not achieve strict preservation. The design modification flow detects this preservation failure.