AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

ID 683720
Date 9/01/2018
Document Table of Contents

Preparing the Design Example in the Intel® Quartus® Prime Software

Install the Intel® Quartus® Prime Standard Edition software v17.0.2.
  1. Obtain from the Intel Functional Safety webpage and extract the files to your PC.
    Figure 11. Directory Structure
  2. In the Intel® Quartus® Prime software, open the DOC_top.qpf project file from the project directory
  3. On the Tools menu, click Qsys.
  4. Open the Qsys System DOC_Single_Axis_FE2H_CVE.qsys .
  5. Click Generate > Generate HDL > .
  6. In Intel® Quartus® Prime, before you specify any partition settings, compile the complete design: click Processing > Start > Start Analysis and Elaboration
  7. View the design hierarchy in the Project Navigator.