AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

ID 683720
Date 9/01/2018
Document Table of Contents

Assigning I/O Pins

You should consider all I/O pins that connect to a safety IP to be included in the safety IP partition.

The functional safety separation flow preserves the pin locations and routing to and from the safety IP partition logic. The partially preserved bitstream contains information that IOs are still connected and configured the same as some of the programming bits. If an IO_REG group contains a pin that you assign to a safety IP, the Intel® Quartus® Prime software exclusively reserves all pins in the IO_REG group for this safety IP. Because an IO register bank contains 16 pins, this restriction can potentially waste pins.

  1. If this restriction causes pin assignment problems with other partitions because of unused pins in safety IP IO_REG groups, preallocate unused I/O pins in the safety IP IO_REG group, so other partitions can use them.
  2. Connect unused pins to the safety IP, which pass through to internal ports.
    To enable a signal to go through a Safety IP partition, add input and output ports to the HDL for the partition to allow the non-safe signal to pass through and ensure some logic, which the synthesis tool does not optimize away. The simplest logic that you can add is a wire-lut, by using a synthesis keep command on the signal that passes through the Safety IP. You can connect these pins to nonsafety IP partitions without requiring changes to the safety IP.
Figure 7. Tunnel Nonsafety IP Signal Through Safety IP Region Sharing unused pins in a safe IO register bank with a non-safety IP partition