AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

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ID 683720
Date 9/01/2018
Public
Document Table of Contents
Document Table of Contents x
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification x
About the Functional Safety Separation Flow Work Flows Functional Safety Separation of a Motor Control Design Example Appendix A: Terminology Appendix B: Design Checklist Document Revision History for AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
Work Flows x
Design Creation Flow Design Modification Flow
Functional Safety Separation of a Motor Control Design Example x
Design Considerations Design Creation Flow Using the Design Modification Flow
Design Considerations x
About Safety IP Partitions and LogicLock Regions Assigning I/O Pins Clocks, PLLs and Resets Routing Across Safety IP Partitions
Design Creation Flow x
Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Using the Intel® Quartus® Prime Incremental Compilation x
Creating a Partition for the FOC Fixed-Point Component Creating a LogicLock Region for the FOC Fixed-Point Component
Generating Safety IP Bitstream Files x
Generating Complete FPGA Bitstream File
Using the Design Modification Flow x
Changing Nonsafety IP - Changing FOC Algorithm Parameter Adding New Features to Nonsafety IP Importing Safety IP Partition
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

Assigning I/O Pins

You should consider all I/O pins that connect to a safety IP to be included in the safety IP partition.

The functional safety separation flow preserves the pin locations and routing to and from the safety IP partition logic. The partially preserved bitstream contains information that IOs are still connected and configured the same as some of the programming bits. If an IO_REG group contains a pin that you assign to a safety IP, the Intel® Quartus® Prime software exclusively reserves all pins in the IO_REG group for this safety IP. Because an IO register bank contains 16 pins, this restriction can potentially waste pins.

  1. If this restriction causes pin assignment problems with other partitions because of unused pins in safety IP IO_REG groups, preallocate unused I/O pins in the safety IP IO_REG group, so other partitions can use them.
  2. Connect unused pins to the safety IP, which pass through to internal ports.
    To enable a signal to go through a Safety IP partition, add input and output ports to the HDL for the partition to allow the non-safe signal to pass through and ensure some logic, which the synthesis tool does not optimize away. The simplest logic that you can add is a wire-lut, by using a synthesis keep command on the signal that passes through the Safety IP. You can connect these pins to nonsafety IP partitions without requiring changes to the safety IP.
Figure 7. Tunnel Nonsafety IP Signal Through Safety IP Region Sharing unused pins in a safe IO register bank with a non-safety IP partition


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