AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

ID 683720
Date 9/01/2018
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Clocks, PLLs and Resets

Consider carefully clocks and their associated resets for a safety IP. PLLs often generate clocks in the FPGA using an external reference clock source. To preserve the PLL configuration and clock routing in the safety IP, optionally include the PLL in the safety IP partition. However, clocks and resets often require additional safety checking measures to ensure the safety IP is operating to specification. These measures may include clock checking functionality.
Figure 8. PLL and Safety IP Placement (Red)
Note: The Intel® Quartus® Prime software preserves the routing to and from the PLL in the partially preserved bitstream

After a design creation flow compliation, the Intel® Quartus® Prime software fixes all routing for the safety IP. Ensure that the design's clock networks allow the flexibility the design requires for the design modification flow. If necessary, assign clock networks manually and consider manually adding altclkctrl buffers to the safety IP to increase PLL placement flexibility.