AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

ID 683720
Date 9/01/2018
Document Table of Contents

About the Functional Safety Separation Flow

This flow extends the widely-adopted, proven Intel® Quartus® Prime incremental compilation flow, which reduces compilation times by up to 70% through logic preservation.

The incremental compilation flow maps the design hierarchy to design partitions that the Intel® Quartus® Prime software treats separately during compilation. Intel defines a design partition as a logical partition. You use logical partitions with a physical placement constraint, a LogicLock region, to form the foundation for the safety flow.

In the functional safety separation flow, you categorize design partitions as either safety IP, which require complete preservation, or nonsafety IP. To configure a safety IP partition, set the partitions Strict preservation setting to On.

When you declare a design partition, every hierarchy within that partition becomes part of the same partition. When you create new partitions for hierarchies within an existing partition, the logic within the new lower-level partition is no longer part of the higher-level partition.

Figure 1. Partitions in a Design Hierarchy B and F-G are design partitions. Partition B includes entity B which contains sub-entities D and E. Partition F-G includes entities F and G. The default partition, top, contains entities A and C which are not assigned to any other partition.

Figure 2. LogicLock Regions for Partitions in a Design Hierarchy

Use a LogicLock region to create a physical placement constraint for the logical partition B.