Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Generating Complete FPGA Bitstream File
- When generating the final FPGA programming bitstream with quartus_cpf, use the generate_signature option to generate an MD5.sign file containing the MD5 checksum. Store the checksum as evidence of the flow
.e.g. quartus_cpf -c -o generate_signature=on <design>.sof <fpgabitstream>.rbf
- The final FPGA programming bitstream generated by quartus_cpf may be encrypted or unencrypted. The partialy preserved bitstream files (.rbf.ppb) generated by quartus_cpf are always unencrypted. To encrypt a bitstream use the quartus_cpf --key option.
e.g. quartus_cpf -c -o generate_signature=on --key test.key:key1 <design>.sof <encryptedfpgabitstream>.rbf
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