Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
DC Link Monitor safety IP partition
A safety IP partition may contain safety logic only. The DC link monitor measures the DC Link voltage in the drive system and requests a shutdown of the system if it is out of tolerance. The block only has one data input from the sigma-delta ADC on the power board. However the ADC also requires a 20MHz clock output, generated from the FPGA PLL, to operate. Therefore, the safety IP partition includes both the DC link monitor and the PLL. In this design example, a separate Qsys subsystem contains the PLL and DC link monitor and has a safety IP partition for the created subsystem. The Qsys system exports the PLL generated clocks from the safety IP partition so other partitions may use them.