Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Creating a LogicLock Region for the PWM Interface
- Create a new LogicLock region.
- In the Project Navigator, right-click on the entity DOC_Single_Axis_FE2H_CVE_ drive0:drive0 > ssg_emb_pwm:doc_pwm
- Click LogicLock Region > Create New LogicLock Region
- Open the LogicLock Regions window:
- In the Project Navigator, select the entity DOC_Single_Axis_FE2H_CVE_ drive0:drive0 > ssg_emb_pwm:doc_pwm
- Right-click and select LogicLock Region > LogicLock Regions Window.
- Set a fixed size and origin for the safety IP partition:
- In the LogicLock Regions window, right-click the region DOC_Single_Axis_FE2H_CVE_ drive0:drive0 > ssg_emb_pwm:doc_pwm
- Select LogicLock Regions Properties
- Turn on Reserved (Prevent Fitter from placing non-member logic in region).
- On the Size and Origin tab, choose a fixed size and origin for the region. You may select your own values, however width = 7, height = 5, origin = X74_Y45 are suitable values.
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