AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

ID 683720
Date 9/01/2018
Public
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Creating a LogicLock Region for the PWM Interface

  1. Create a new LogicLock region.
    1. In the Project Navigator, right-click on the entity DOC_Single_Axis_FE2H_CVE_ drive0:drive0 > ssg_emb_pwm:doc_pwm
    2. Click LogicLock Region > Create New LogicLock Region
  2. Open the LogicLock Regions window:
    1. In the Project Navigator, select the entity DOC_Single_Axis_FE2H_CVE_ drive0:drive0 > ssg_emb_pwm:doc_pwm
    2. Right-click and select LogicLock Region > LogicLock Regions Window.
  3. Set a fixed size and origin for the safety IP partition:
    1. In the LogicLock Regions window, right-click the region DOC_Single_Axis_FE2H_CVE_ drive0:drive0 > ssg_emb_pwm:doc_pwm
    2. Select LogicLock Regions Properties
    3. Turn on Reserved (Prevent Fitter from placing non-member logic in region).
    4. On the Size and Origin tab, choose a fixed size and origin for the region. You may select your own values, however width = 7, height = 5, origin = X74_Y45 are suitable values.