AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

ID 683720
Date 9/01/2018
Document Table of Contents

Design Creation Flow

This flow defines the necessary steps for initial design creation in a way that allows you to modify the nonsafety IP in your design without recertifying the safety IP. Some of the steps are architectural constraints. You need to perform the remaining steps in the Intel® Quartus® Prime software. You use the design creation flow for the first pass certification of your product.

The Intel FPGA development V-Model stage refers to the V-Model stages described in the Intel FPGA V-flow that Intel's Functional Safety Data Pack includes

When you make modifications to the safety IP in your design, you must use the design creation flow.
Figure 4. Design Creation Flow