Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Design Creation Flow
This flow defines the necessary steps for initial design creation in a way that allows you to modify the nonsafety IP in your design without recertifying the safety IP. Some of the steps are architectural constraints. You need to perform the remaining steps in the Intel® Quartus® Prime software. You use the design creation flow for the first pass certification of your product.
The Intel FPGA development V-Model stage refers to the V-Model stages described in the Intel FPGA V-flow that Intel's Functional Safety Data Pack includes
When you make modifications to the safety IP in your design, you must use the design creation flow.
Figure 4. Design Creation Flow
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