Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
The architecture and design hierarchy options for an industrial system with functional safety requirements are vast, and coupled closely to the application. In this example, the safety IP partitions demonstrate the design flow in the context of multiple partitions and hierarchical partitions with associated clocking structures, PLLs, and IO pins.
This application note does not recommend which IP you should categorize as safety IP and nonsafety IP.
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