AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

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ID 683720
Date 9/01/2018
Public
Document Table of Contents
Document Table of Contents x
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification x
About the Functional Safety Separation Flow Work Flows Functional Safety Separation of a Motor Control Design Example Appendix A: Terminology Appendix B: Design Checklist Document Revision History for AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
Work Flows x
Design Creation Flow Design Modification Flow
Functional Safety Separation of a Motor Control Design Example x
Design Considerations Design Creation Flow Using the Design Modification Flow
Design Considerations x
About Safety IP Partitions and LogicLock Regions Assigning I/O Pins Clocks, PLLs and Resets Routing Across Safety IP Partitions
Design Creation Flow x
Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Using the Intel® Quartus® Prime Incremental Compilation x
Creating a Partition for the FOC Fixed-Point Component Creating a LogicLock Region for the FOC Fixed-Point Component
Generating Safety IP Bitstream Files x
Generating Complete FPGA Bitstream File
Using the Design Modification Flow x
Changing Nonsafety IP - Changing FOC Algorithm Parameter Adding New Features to Nonsafety IP Importing Safety IP Partition
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

Creating a Safety IP partition for the PWM Interface Component

  1. In the Project Navigator, expand the DOC_Single_Axis_FE2H_CVE:u_doc hierarchy
  2. Select the entity DOC_Single_Axis_FE2H_CVE_drive0:drive0 > ssg_emb_pwm:doc_pwm
  3. Right-click and select Design Partition > Set as Design Partition.
  4. Confirm a partition icon appears next to the doc_pwm entity.
  5. Open the Design Partition Window:
    1. In the Project Navigator, select the entity DOC_Single_Axis_FE2H_CVE_drive0:drive0 > ssg_emb_pwm:doc_pwm
    2. Right-click and select Design Partition > Design Partition Window.
  6. Ensure you strictly preserve the design partition, as required by the safety separation flow
    1. In the Design Partition Window, right-click the ssg_emb_pwm:doc_pwm partition and select Design Partition Properties…
    2. Set the partition netlist type to Post-Fit.
    3. On the Strict Preservation tab, turn on Allow partition to be strictly preserved for safety.
    4. On the Advanced tab set the "Fitter Preservation Level" to "Placement and Routing"
  7. Add the following assignments to the .qsf file, to set the pin assignment. 
    set_instance_assignment -name ENABLE_STRICT_PRESERVATION ON -to drive0_pwm_u_h -section_id "ssg_emb_pwm:doc_pwm"

set_instance_assignment -name ENABLE_STRICT_PRESERVATION ON -to drive0_pwm_u_l -section_id "ssg_emb_pwm:doc_pwm"

set_instance_assignment -name ENABLE_STRICT_PRESERVATION ON -to drive0_pwm_v_h -section_id "ssg_emb_pwm:doc_pwm"

set_instance_assignment -name ENABLE_STRICT_PRESERVATION ON -to drive0_pwm_v_l -section_id "ssg_emb_pwm:doc_pwm"

set_instance_assignment -name ENABLE_STRICT_PRESERVATION ON -to drive0_pwm_w_h -section_id "ssg_emb_pwm:doc_pwm"

set_instance_assignment -name ENABLE_STRICT_PRESERVATION ON -to drive0_pwm_w_l -section_id "ssg_emb_pwm:doc_pwm"
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