Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

System-Level Debugging Infrastructure

On‑chip debugging tools that require the JTAG resources share two Data Register chain paths; USER1 and USER0 instructions select the Data Register chain paths. The datapaths are an extension of the JTAG circuitry for use with the programmable logic elements in Intel® devices.

Because the JTAG resource is shared among multiple on-chip applications, an arbitration scheme must define how the USER0 and USER1 scan chains are allocated between the different applications. The system-level debugging (SLD) infrastructure defines the signaling convention and the arbitration logic for all programmable logic applications using a JTAG resource. The figure below shows the SLD infrastructure architecture.

Figure 5. System Level Debugging Infrastructure Functional Model

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