In its implementation, the Virtual JTAG Intel® FPGA IP core connects to your design on one side and to the JTAG port through the JTAG hub on the other side. However, a simulation model connects only to your design. There is no simulation model for the JTAG circuit. Therefore, no stimuli can be provided from the JTAG ports of the device to imitate the scan shift operations of the Virtual JTAG Intel® FPGA IP core in simulation.
The scan operations in simulation are realized using the simulation model. The simulation model consists of a signal generator, a model of the SLD hub, and the Virtual JTAG model. The stimuli defined in the wizard are passed as parameters to this simulation model from the variation file. The simulation parameters are listed in the table below. The signal generator then produces the necessary signals for Virtual JTAG Intel® FPGA IP core outputs such as tck, tdi, tms, and so forth.
The model is parameterized to allow the simulation of an unlimited number of Virtual JTAG instances. The parameter sld_sim_action defines the strings used for IR and DR scan shifts. Each Virtual JTAG’s variation file passes these parameters to the Virtual JTAG component. The Virtual JTAG’s variation file can always be edited for generating different stimuli, though the preferred way to specify stimuli for DR and IR scan shifts is to use the parameter editor.
Specifies the number of shifts in the simulation model.
The total number of bits to be shifted in either an IR shift or a DR shift. This value should be equal to the sum of all the length values specified in the sld_sim_action string.
Specifies the strings used for instruction register (IR) and data register (DR) scan shifts. The string has the following format:
Entries are in hexadecimal format.
Simulation has the following limitations:
- Scan shifts (IR or DR) must be at least 1 ms apart in simulation time.
- Only behavioral or functional level simulation support is present for this IP core. There is no gate level or timing level simulation support.
- For behavioral simulation, the stimuli tell the signal generator model in the Virtual JTAG model to generate the sequence of signals needed to produce the necessary outputs for tck, tms, tdi, and so forth. You cannot provide the stimulus at the JTAG pins of the device.
- The tck clock period used in simulation is 10 MHz with a 50% duty cycle. In hardware, the period of the tck clock cycle may vary.
- In a real system, each instance of the Virtual JTAG Intel® FPGA IP core works independently. In simulation, multiple instances can work at the same time. For example, if you define a scan shift for Virtual JTAG instance number 1 to happen at 3 ms and a scan shift for Virtual JTAG instance number 2 to happen at the same time, the simulation works correctly.
If you are using the ModelSim* - Intel® FPGA Edition simulator, the altera_mf.v and altera_mf.vhd libraries are provided in precompiled form with the simulator.
The inputs and outputs of the Virtual JTAG Intel® FPGA IP core during a typical IR scan shift operation are shown in the figure below.
The figure below shows the inputs and outputs of the Virtual JTAG Intel® FPGA IP core during a typical DR scan shift operation.
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