Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

Simulation Support

Virtual JTAG interface operations can be simulated using all Intel‑supported simulators. The simulation support is for DR and IR scan shift operations. For simulation purposes, a behavioral simulation model of the IP core is provided in both VHDL and Verilog HDL in the altera_mf libraries. The I/O structure of the model is the same as the IP core.

In its implementation, the Virtual JTAG Intel® FPGA IP core connects to your design on one side and to the JTAG port through the JTAG hub on the other side. However, a simulation model connects only to your design. There is no simulation model for the JTAG circuit. Therefore, no stimuli can be provided from the JTAG ports of the device to imitate the scan shift operations of the Virtual JTAG Intel® FPGA IP core in simulation.

The scan operations in simulation are realized using the simulation model. The simulation model consists of a signal generator, a model of the SLD hub, and the Virtual JTAG model. The stimuli defined in the wizard are passed as parameters to this simulation model from the variation file. The simulation parameters are listed in the table below. The signal generator then produces the necessary signals for Virtual JTAG Intel® FPGA IP core outputs such as tck, tdi, tms, and so forth.

The model is parameterized to allow the simulation of an unlimited number of Virtual JTAG instances. The parameter sld_sim_action defines the strings used for IR and DR scan shifts. Each Virtual JTAG’s variation file passes these parameters to the Virtual JTAG component. The Virtual JTAG’s variation file can always be edited for generating different stimuli, though the preferred way to specify stimuli for DR and IR scan shifts is to use the parameter editor.

Note: To perform functional and timing simulations, you must use the altera_mf.v library located in the < Quartus® Prime installation directory>\eda\sim_lib directory. For VHDL, you must use the altera_mf.vhd library located in the < Quartus® Prime installation directory>\eda\sim_lib directory. The VHDL component declaration file is located in the altera_mf_components.vhd library in the < Quartus® Prime installation directory>\eda\sim_lib directory.
Table 9.  Description of Simulation Parameters

Parameter

Comments

sld_sim_n_scan

Specifies the number of shifts in the simulation model.

sld_sim_total_length

The total number of bits to be shifted in either an IR shift or a DR shift. This value should be equal to the sum of all the length values specified in the sld_sim_action string.

sld_sim_action

Specifies the strings used for instruction register (IR) and data register (DR) scan shifts. The string has the following format: 

((time,type,value,length),
(time,type,value,length),
 ...
(time,type,value,length))

where:

  • time—A 32-bit value in milliseconds that represents the start time of the shift relative to the completion of the previous shift.
  • type—A 4-bit value that determines whether the shift is a DR shift or an IR shift.
  • value—The data associated with the shift. For IR shifts, it is a 32-bit value. For DR shifts, the length is determined by length.
  • length—A 32-bit value that specifies the length of the data being shifted. This value should be equal to SLD_NODE_IR_WIDTH; otherwise, the value field may be padded or truncated. 0 is invalid.

Entries are in hexadecimal format.

Simulation has the following limitations:

  • Scan shifts (IR or DR) must be at least 1 ms apart in simulation time.
  • Only behavioral or functional level simulation support is present for this IP core. There is no gate level or timing level simulation support.
  • For behavioral simulation, the stimuli tell the signal generator model in the Virtual JTAG model to generate the sequence of signals needed to produce the necessary outputs for tck, tms, tdi, and so forth. You cannot provide the stimulus at the JTAG pins of the device.
  • The tck clock period used in simulation is 10 MHz with a 50% duty cycle. In hardware, the period of the tck clock cycle may vary.
  • In a real system, each instance of the Virtual JTAG Intel® FPGA IP core works independently. In simulation, multiple instances can work at the same time. For example, if you define a scan shift for Virtual JTAG instance number 1 to happen at 3 ms and a scan shift for Virtual JTAG instance number 2 to happen at the same time, the simulation works correctly.

If you are using the ModelSim* - Intel® FPGA Edition simulator, the altera_mf.v and altera_mf.vhd libraries are provided in precompiled form with the simulator.

The inputs and outputs of the Virtual JTAG Intel® FPGA IP core during a typical IR scan shift operation are shown in the figure below.

Figure 14. IR Shift Waveform

The figure below shows the inputs and outputs of the Virtual JTAG Intel® FPGA IP core during a typical DR scan shift operation.

Figure 15. DR Shift Waveform
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