Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

AHDL Function Prototype

The following AHDL function prototype is located in the sld_virtual_jtag.inc file in the < Intel® Quartus® Prime installation directory> \libraries\megafunctions directory.
Note:

Port name and order also apply to Verilog HDL. 

FUNCTION sld_virtual_jtag(
        ir_out[sld_ir_width-1..0],

        tdo
)

WITH(
        lpm_hint,
        lpm_type,
        sld_auto_instance_index,
        sld_instance_index,
        sld_ir_width,
        sld_sim_action,
        sld_sim_n_scan,
        sld_sim_total_length
)
RETURNS(
        ir_in[sld_ir_width-1..0],
        jtag_state_cdr,
        jtag_state_cir,
        jtag_state_e1dr,
        jtag_state_e1ir,
        jtag_state_e2dr,
        jtag_state_e2ir,
        jtag_state_pdr,
        jtag_state_pir,
        jtag_state_rti,
        jtag_state_sdr,
        jtag_state_sdrs,
        jtag_state_sir,
        jtag_state_sirs,
        jtag_state_tlr,
        jtag_state_udr,
        jtag_state_uir,
        tck,
        tdi,
        tms,
        virtual_state_cdr,
        virtual_state_cir,
        virtual_state_e1dr,
        virtual_state_e2dr,
        virtual_state_pdr,
        virtual_state_sdr,
        virtual_state_udr,
        virtual_state_uir
);
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