Virtual JTAG Intel® FPGA IP Core User Guide

Download PDF
ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

SLD_NODE Info Register

When the number of SLD nodes is known, the nodes on the hub can be enumerated by repeating the 8 four-bit nibble scans, once for each Node, to yield the SLD_NODE_INFO register of each node.

The DR nibble shifts are a continuation of the HUB_INFO DR shift used to shift out the Hub IP Configuration register.

The order of the Nodes as they are shifted out determines the ADDR values for the Nodes, beginning with, for the first Node SLD_NODE_INFO shifted out, up to and including, for the last node on the hub. The tables below show the SLD_NODE_INFO register and their functional descriptions.

Table 13.  SLD_NODE_INFO Register

31

27

26

19

18

8

7

0

Node Version

NODE ID

NODE MFG_ID

NODE_INST_ID

Table 14.  SLD_NODE_INFO Register Descriptions

Field

Function

Node Version

Identifies the version of the SLD node

NODE ID

Identifies the type of NODE IP (0x8 for the Virtual JTAG Intel® FPGA IP core)

NODE MFG_ID

SLD Node Manufacturer ID (0x6E for Virtual JTAG Intel® FPGA IP core)

NODE_INST_ID

Used to distinguish multiple instances of the same IP. Corresponds to the instance index assigned in the parameter editor.

You can identify each Virtual JTAG instance within the design by decoding NODE ID and NODE_INST_ID. The Virtual JTAG Intel® FPGA IP core uses a NODE ID of 8. The NODE_INST_ID corresponds to the instance index that you configured within the parameter editor. The ADDR bits for each Virtual JTAG node is then determined by matching each Virtual JTAG instance to the sequence number in which the SLD_NODE_INFO register is shifted out.

Level Two Title