Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

Write Logic

The RTL uses a single instance of the Virtual JTAG Intel® FPGA IP core to decode both the instructions for the write side and read side logic. The IR register is three bits wide, with the three instructions decoded in the RTL, as shown in the table below.
Table 16.  Instruction Register Values

Instruction Register Value



Instruction to write a single value to the write side logic of the DCFIFO.


Instruction to read a single value from the read side logic of the DCFIFO


Instruction to perform a burst read transaction from the FIFO until empty.

The IR decode logic shifts the Push_in virtual DR chain when the PUSH instruction is on the IR port and virtual_state_sdr is asserted. A write enable pulse, synchronized to the write_clock, asserts after the virtual_state_udr signal goes high. The virtual_state_udr signal guarantees stability from the virtual DR chain. The figure below shows the write side logic for the DCFIFO.

Figure 20. Write Side Logic for DCFIFO