Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

Design Example: Offloading Hardwired Revision Information

This example demonstrates how you can use a GUI to offload revision information that is hardwired into a design. The GUI offloads the time that the design was compiled, the USERCODE from the device, and compile number that tracks the number of compile iterations that have been performed.

Because the Quartus® Prime software ships with an installation of Tcl/Tk, you can use the Tk package to build a custom GUI to interact with your design. In many cases, the JTAG port is a convenient interface to use, since it is present in most designs for debug purposes. By leveraging Tk and the virtual JTAG interface, you perform rapid prototyping such as creating virtual front panels or creating simple software applications. The figure below shows the organization of the design.

Figure 24. Design Organization Example

A Tcl script creates and updates the verilog file containing the hard­coded version control information every time the project goes through a full compile. The Tcl script is executed automatically by adding the following assignment to the project’s .qsf file.

The USERCODE value shifted out by this design example is a user‑configurable 32-bit JTAG register. This value is configured in the Quartus® Prime software using the Device and Pin Options dialog box.