Design Example: Modifying the DCFIFO Contents at Runtime
The Tcl API that ships with the Virtual JTAG Intel® FPGA IP core makes it an ideal solution for developing command‑line scripts that can be used to either update data values or toggle control bits at run time. This visibility into the FPGA can help expedite debug closure during the prototyping phase of the design, especially when external equipment is not available to provide a stimulus.
This design example consists of an Intel® Quartus® Prime project file that implements a DCFIFO and a command‑line script that is used to modify the contents of the FIFO at runtime.
The RTL consists of a single instantiation of the Virtual JTAG Intel® FPGA IP core to communicate with the JTAG circuitry. Both read and write ports of the DCFIFO are clocked at 50 MHz. A Signal Tap logic analyzer instance taps the data output bus of the DCFIFO to read burst transactions from the DCFIFO. The following sections discuss the RTL implementation and the runtime control of the DCFIFO using the Tcl API.
Did you find the information on this page useful?