Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

Design Example: TAP Controller State Machine

The TAP controller is a state machine with a set of control signals that routes TDI data between the Instruction Register and the bank of DR chains. It controls the start and stop of any shift transactions, and controls the data flow between the parallel hold registers and the shift registers of the Instruction Register and the Data Register. The TAP controller is controlled by the TMS pin.

The figure below shows the TAP controller state machine. The table that follows provides a description of each of the states.

Figure 19. JTAG TAP Controller State Machine
Table 15.  Functional Description for the TAP Controller States

TAP Controller State

Functional Description

Test-Logic-Reset

The test logic of the JTAG scan chain is disabled.

Run-Test/Idle

This is a hold state. Once entered, the controller remains in this state as long as TMS is held low.

Select DR-Scan/Select IR Scan

These are temporary controller states. A decision is made here whether to enter the DR states or the IR states.

Capture DR/Capture IR

These states enable a parallel load of the shift registers from the hold registers on the rising edge of TCK.

Shift DR/Shift IR

These states enable shifting of the DR and IR chains.

Exit1 DR/Exit1 IR

Temporary hold states. A decision is made in these states to either advance to the Update states or the Pause states.

Pause DR/Pause IR

This controller state allows shifting of the Instruction Register and Data Register to be temporarily halted.

Exit2 DR/Exit2 IR

Temporary hold states. A decision is made in these states to advance to the Update states.

Update DR/Update IR

These states enable a parallel load of the hold registers from the shift registers. Update happens on the falling edge of TCK.

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