Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

Capturing the Virtual IR Instruction Register

In applications that contain multiple nodes, capturing the value of the VIR may require issuing an instruction to the SLD hub to target a SLD node. You can query for a VIR using the VIR_CAPTURE instruction.

Each NODE VIR register acts as a parallel hold rank register to the USER1 DR chain. The sld_hub uses the bits prepended to the VIR shift value to target the correct SLD NODE VIR register. After the SLD_state_machine asserts virtual_update_IR, the active SLD node latches VIR_VALUE of the USER1 DR register.

The figure below shows a functional model of the interaction of the USER1 DR register and the SLD node VIR. The ADDR bits target the selection muxes in the figure after the sld_hub FSM has exited the virtual_update_IR state. Upon the next USER1 DR transaction, the USER1 DR chain will latch the VIR of the last active SLD_NODE to shift out of TDO. Thus, if you need to capture the VIR of an SLD node that is different than the one addressed in the previous shift cycle, you must issue the VIR_CAPTURE instruction. The VIR_CAPTURE instruction to the sld_hub acts as an address cycle to force an update to the muxes.

Figure 18. Functional Model Interaction between USER1 DR CHAIN and SLD Node VIRs

To form the VIR_CAPTURE instruction, use the following instruction format:

VIR_CAPTURE = ZERO [ (m – 4)..0] ## ADDR [(n – 1)..0] ## 011

In this format, ZERO[] is an array of zeros, ## is the concatenation operator, m is the width of VIR_VALUE, and n is the width of the ADDR bit.

Did you find the information on this page useful?

Characters remaining:

Feedback Message