Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

Simulation Model

The virtual JTAG Intel® FPGA IP core contains a functional simulation model that provides stimuli that mimic VIR and VDR shifts. You can configure the stimuli using the parameter editor. You can use this simulation model for functional verification only, and the operation of the SLD hub and the SLD node-to-hub interface is not provided in this simulation model.