Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

Output Ports

Table 3.  Output Ports for the Virtual JTAG Intel® FPGA IP Core
Port Name Required Description Comments
tck Yes JTAG test clock. Connected directly to the TCK device pin. Shared among all virtual JTAG instances.
tdi Yes TDI input data on the device. Used when virtual_state_sdr is high. Shared among all virtual JTAG instances.
ir_in[] No Virtual JTAG instruction register data. The value is available and latched when virtual_state_uir is high. Output port [SLD_IR_WIDTH-1..0] wide. Specify the width of this bus with the SLD_IR_WIDTH parameter.
Table 4.  High-Level Virtual JTAG State Signals
Port Name Required Description Comments
virtual_state_cdr No

Indicates that virtual JTAG is in Capture_DR state.

virtual_state_sdr Yes

Indicates that virtual JTAG is in Shift_DR state.

In this state, this instance is required to establish the JTAG chain for this device.

virtual_state_e1dr No

Indicates that virtual JTAG is in Exit1_DR state.

virtual_state pdr No

Indicates that virtual JTAG is in Pause_DR state.

The Intel® Quartus® Prime software does not cycle through this state using the Tcl command.

virtual_state_e2dr No

Indicates that virtual JTAG is in Exit2_DR state.

The Intel® Quartus® Prime software does not cycle through this state using the Tcl command.

virtual_state_udr No

Indicates that virtual JTAG is in Update_DR state.

virtual_state_cir No

Indicates that virtual JTAG is in Capture_IR state.

virtual_state_uir No

Indicates that virtual JTAG is in Update_IR state.

Table 5.  Low-Level Virtual JTAG State Signals
Port Name Required Description Comments
jtag_state_tlr No

Indicates that the device JTAG controller is in the Test_Logic_Reset state.

Shared among all virtual JTAG instances.

jtag_state_rti No

Indicates that the device JTAG controller is in the Run_Test/Idle state.

Shared among all virtual JTAG instances.

jtag_state_sdrs No

Indicates that the device JTAG controller is in the Select_DR_Scan state.

Shared among all virtual JTAG instances.

jtag_state_cdr No

Indicates that the device JTAG controller is in the Capture_DR state.

Shared among all virtual JTAG instances.

jtag_state_sdr No

Indicates that the device JTAG controller is in the Shift_DR state.

Shared among all virtual JTAG instances.

jtag_state_e1dr No

Indicates that the device JTAG controller is in the Exit1_DR state.

Shared among all virtual JTAG instances.

jtag_state_pdr No

Indicates that the device JTAG controller is in the Pause_DR state.

Shared among all virtual JTAG instances.

jtag_state_e2dr No

Indicates that the device JTAG controller is in the Exit2_DR state.

Shared among all virtual JTAG instances.

jtag_state_udr No

Indicates that the device JTAG controller is in the Update_DR state.

Shared among all virtual JTAG instances.

jtag_state_sirs No

Indicates that the device JTAG controller is in the Select_IR_Scan state.

Shared among all virtual JTAG instances.

jtag_state_cir No

Indicates that the device JTAG controller is in the Capture_IR state.

Shared among all virtual JTAG instances.

jtag_state_sir No

Indicates that the device JTAG controller is in the Shift_IR state.

Shared among all virtual JTAG instances.

jtag_state_e1ir No

Indicates that the device JTAG controller is in the Exit1_IR state.

Shared among all virtual JTAG instances.

jtag_state_pir No

Indicates that the device JTAG controller is in the Pause_IR state.

Shared among all virtual JTAG instances.

jtag_state_e2ir No

Indicates that the device JTAG controller is in the Exit2_IR state.

Shared among all virtual JTAG instances.

jtag_state_uir

Indicates that the device JTAG controller is in the Update_IR state.

Shared among all virtual JTAG instances.

tms

TMS input pin on the device.

Shared among all virtual JTAG instances.

Level Two Title