Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

Input Ports

Table 2.  Input Ports for the Virtual JTAG Intel® FPGA IP Core
Port name Required Description Comments
tdo Yes Writes to the TDO pin on the device.
ir_out[] No Virtual JTAG instruction register output. The value is captured whenever virtual_state_cir is high. Input port [SLD_IR_WIDTH-1..0] wide. Specify the width of this bus with the SLD_IR_WIDTH parameter.

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