Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

Design Flow of the Virtual JTAG Intel® FPGA IP Core

Designing with the Virtual JTAG Intel® FPGA IP core includes the following processes:
  • Configuring the Virtual JTAG Intel® FPGA IP core with the desired Instruction Register length and instantiating the IP core.
  • Building the glue logic for interfacing with your application.
  • Communicating with the Virtual JTAG instance during runtime.

In addition to the JTAG datapath and control signals, the Virtual JTAG Intel® FPGA IP core encompasses the VIR. The Instruction Register size is configured in the parameter editor. The Instruction Register port on the Virtual JTAG Intel® FPGA IP core is the parallel output of the VIR. Any updated VIR information can be read from this port after the virtual_state_uir signal is asserted.

After instantiating the IP core, you must create the VDR chains that interface with your application. To do this, you use the virtual instruction output to determine which VDR chain is the active datapath, and then create the following:

  • Decode logic for the VIR
  • VDR chains to which each VIR maps
  • Interface logic between your VDR chains and your application logic

Your glue logic uses the decoded one-hot outputs from the IP core to determine when to shift and when to update the VDR. Your application logic interfaces with the VDR chains during any one of the non-shift virtual JTAG states.

For example, your application logic can parallel read an updated value that was shifted in from the JTAG port after the virtual_state_uir signal is asserted. If you load a value to be shifted out of the JTAG port, you would do so when the virtual_state_cdr signal is asserted. Finally, if you enable the shift register to clock out information to TDO, you would do so during the assertion of virtual_state_sdr.

Maintaining TDI‑to‑TDO connectivity is important. Ensure that all possible instruction codes map to an active register chain to maintain connectivity in the TDI‑to‑TDO datapath. Intel recommends including a bypass register as the active register for all unmapped IR values.

Note that TCK (a maximum 10‑MHz clock, if using an Intel® programming cable) provides the clock for the entire SLD infrastructure. Be sure to follow best practices for proper clock domain crossing between the JTAG clock domain and the rest of your application logic to avoid metastability issues. The decoded virtual JTAG state signals can help determine a stable output in the VIR and VDR chains.

After compiling and downloading your design into the device, you can perform shift operations directly to the VIR and VDR chains using the Tcl commands from the quartus_stp executable and an Intel® programming cable (for example, an Intel® FPGA Download Cable, a MasterBlaster™ cable, or an Intel® FPGA Parallel Port Cable). The quartus_stp executable is a command‑line executable that contains Tcl commands for all on‑chip debug features available in the Quartus® Prime software.

The figure below shows the components of a design containing one instance of the Virtual JTAG Intel® FPGA IP core. The TDI-to-TDO datapath for the virtual JTAG chain, shown in red, consists of a bank of DR registers. Input to the application logic is the parallel output of the VDR chains. Decoded state signals are used to signal start and stop of shift transactions and signals when the VDR output is ready.

The IR_out port, not shown, is an optional input port you can use to parallel load the VIR from the FPGA core logic.

Figure 9. Block Diagram of a Design with a Single Virtual JTAG Instantiation