Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide

Document Version Quartus® Prime Version Changes
2021.08.12 20.3 Corrected the table title to: USER0 and USER1 Instruction Values in the SLD_NODE Discovery and Enumeration section.
2020.12.01 20.3
  • Changed table title from Virtual JTAG Settings Description to Parameter Settings for Virtual JTAG and updated the content.
  • Updated parameters in the Description of Simulation Parameters table.
  • Updated the description in the Compiling the Design section.
  • Updated the following diagrams:
    • Compilation Report
    • IDs of Virtual JTAG Instances
    • Logic Resources Utilization
  • Renamed IP from Virtual JTAG (altera_virtual_jtag) IP core to Virtual JTAG Intel® FPGA IP core.
2018.07.19 16.1
  • Updated the following terms:
    • Changed Quartus II to Intel Quartus Prime.
    • Changed SignalTap II to Signal Tap.
    • Changed megafunction to Intel FPGA IP core.
    • Changed USB Blaster to Intel FPGA Download Cable.
    • Changed ByteBlaster II to Intel FPGA Parallel Port Cable.
    • Changed ModelSim-Altera to ModelSim - Intel FPGA Edition.
  • Rebranded as Intel.




October 2016 2016.10.31 Removed Upgrading IP Cores section.
November 2015 2015.11.20 Corrected the flow for EXIT2_DR to SHIFT_DR in the JTAG TAP Controller State Machine figure.
July 2014 2014.07.08
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.

March 2014


Updated the description of the SLD_IR_WIDTH parameter in the "Parameters for the Virtual JTAG Megafunction" table.

February 2014


  • Added Document Revision History table.
  • Updated "Hub IP Configuration Register" figure.