Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

Read Logic

Two runtime instructions read the contents out of the FIFO. The IR decode logic selects the Push_out virtual DR chain and generates a single read pulse to the read logic when the POP instruction is active. The Push_out DR chain is parallel loaded upon the assertion of virtual_state_cdr and shifted out to TDO upon the assertion of virtual_state_sdr.

When the FLUSH instruction is shifted into the Virtual JTAG instance, the IR decode logic asserts the read_req line until the FIFO is empty. The bypass register is selected when the FLUSH instruction is active to maintain TDI‑to‑TDO connectivity. The figure below shows the read side logic for the DCFIFO.

Figure 21. Read Side Logic for DCFIFO Design Example