During boundary scan testing, software shifts out test data over the serial interface to the BSCs of select ICs. This test data forces a known pattern to the pins connected to the affected BSCs. If the adjacent IC at the other end of the PCB trace is JTAG‑compliant, the BSC of the adjacent IC samples the test pattern and feeds the BSCs back to the software for analysis. The figure below illustrates the boundary-scan testing concept.
Because the JTAG interface shifts in any information to the device, leaves a low footprint, and is available on all Intel® devices, it is considered a general purpose communication interface. In addition to boundary scan applications, Intel® devices use the JTAG port for other applications, such as device configuration and on‑chip debugging features available in the Intel® Quartus® Prime software.
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