Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

Virtual JTAG Interface Description

The Virtual JTAG Interface implements an SLD node interface, which provides a communication interface to the JTAG port. The IP core exposes control signals that are part of the SLD hub; namely, JTAG port signals, all finite state machine controller states of the TAP controller, and the SLD hub finite state machine. Additionally, each instance of the Virtual JTAG Intel® FPGA IP cores contain the virtual Instruction Register for the SLD node. Instantiation of this IP core automatically infers the SLD infrastructure, and one SLD node is added for each instantiation.

The Virtual JTAG Intel® FPGA IP core provides a port interface that mirrors the actual JTAG ports. The interface contains the JTAG port pins, a one‑hot decoded output of all JTAG states, and a one-hot decoded output of all the virtual JTAG states. Virtual JTAG states are the states decoded from the SLD hub finite state machine. The ir_in and ir_out ports are the parallel input and output to and from the VIR. The VIR ports are used to select the active VDR datapath. The JTAG states and TMS output ports are provided for debugging purposes only. Only the virtual JTAG, TDI, TDO, and the IR signals are functional elements of the IP core. When configuring this IP core using the parameter editor, you can hide TMS and the decoded JTAG states.

The figure below shows the input and output ports of the virtual JTAG Intel® FPGA IP core. The JTAG TAP controller outputs and TMS signals are used for informational purposes only. These signals can be exposed using the Create primitive JTAG state signal ports option in the parameter editor.

Figure 8. Input and Output Ports of the Virtual JTAG Intel® FPGA IP Core

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