Virtual JTAG Intel® FPGA IP Core User Guide

ID 683705
Date 8/12/2021
Document Table of Contents

On-Chip Debugging Tool Suite

The On-Chip Debugging Tool Suite enables real time verification of a design and includes the following tools:
On-Chip Debugging Tool Suite  



Typical Circumstances for Use

Signal Tap Logic Analyzer

Uses FPGA resources to sample tests nodes and outputs the information to the Quartus® Prime software for display and analysis.

You have spare on-chip memory and want functional verification of your design running in hardware.

Signal Probe

Incrementally routes internal signals to I/O pins while preserving the results from your last place-and-route.

You have spare I/O pins and want to check the operation of a small set of control pins using either an external logic analyzer or an oscilloscope.

Logic Analyzer Interface (LAI)

Multiplexes a larger set of signals to a smaller number of spare I/O pins. LAI allows you to select which signals are switched onto the I/O pins over a JTAG connection.

You have limited on-chip memory and have a large set of internal data buses that you want to verify using an external logic analyzer. Logic analyzer vendors, such as Tektronics and Agilent, provide integration with the tool to improve usability.

In-System Memory Content Editor

Displays and allows you to edit on‑chip memory.

You want to view and edit the contents of either the instruction cache or data cache of a Nios® II processor application.

In-System Sources and Probes

Provides a way to drive and sample logic values to and from internal nodes using the JTAG interface.

You want to prototype a front panel with virtual buttons for your FPGA design.

Virtual JTAG Interface

Opens the JTAG interface so that you can develop your own custom applications.

You want to generate a large set of test vectors and send them to your device over the JTAG port to functionally verify your design running in hardware.